The present invention relates to a semiconductor device having impurity layers, respectively serving as a source and a drain, at both lateral sides of agate electrode on the semiconductor substrate, and a method of fabricating the same.
Higher integration of LSIs has been achieved by miniaturizing integrated-circuit elements such as transistors, wirings and the like. Now, the LSI design rule reaches the range of 0.25 μm to 0.18 μm. Even in a logic LSI, transistors on the order of 10,000,000 pieces can be integrated in one chip. To make LSIs more multi-functionally operable at higher speed, it is considered that higher integration will increasingly be desired. It is therefore required to further miniaturize MOS transistors serving as LSI main component elements.
In miniaturization of a MOS transistor, the most important subject is how to solve a so-called short channel effect, i.e., a sudden drop in threshold voltage with the reduction in gate length. To solve this problem, it is most effective to minimize the depth of the impurity diffusion layers respectively serving as a source and a drain (shallow junction of impurity diffusion layers). To reduce the depth of the impurity diffusion layers, it is under examination to use, as a dopant, indium (p-type impurity) or antimony (n-type impurity) small in implantation range, and to activate the impurity by rapid thermal annealing in a short period of time.
On the other hand, the shallow junction of impurity diffusion layers results in increase in the sheet resistance of the impurity diffusion layers. This increases the parasitic resistance of the MOS transistor, contributing to the deterioration of the characteristics of the MOS transistor.
To solve the problem of increase in parasitic resistance, there are formed, on the impurity diffusion layers respectively serving as a source and a drain, high-melting-point metal silicide layers of titanium silicide, cobalt silicide or the like, or high-melting-point metal films of tungsten or the like.
However, when the technique of shallow junction of impurity diffusion layers is combined with the technique of forming, on the impurity diffusion layers, such high-melting-point metal silicide layers or high-melting-point metal films, this disadvantageously increases the junction leak current.
To solve this new problem, the Laid-Open Patent Publication No. H6-77246 proposes a MOS transistor having an elevated source-drain structure.
Referring to FIG. 13(a) to FIG. 13(b), the following description will discuss a method of fabricating such a MOS transistor having an elevated source-drain structure.
As shown in FIG. 13(a), an element separating area 702 and a gate insulating film 703 are formed on a p-type silicon substrate 701, and there is then formed, on the gate insulating film 703, a gate electrode comprising a lower n-type polycrystalline silicon layer 704 and an upper silicon oxide film 705.
As shown in FIG. 13(b), arsenic ions are implanted into the p-type silicon substrate 701 to form low-concentration impurity diffusion layers 707 respectively serving as a source and a drain, and a sidewall spacer 706 made of a silicon oxide film is then formed at the lateral sides of the gate electrode.
As shown in FIG. 13(c), monosilane is thermally decomposed to selectively grow silicon single-crystal films on the p-type silicon substrate 701 at areas exposed from the gate electrode and the sidewall spacer 706, and arsenic ions are then implanted into the silicon single-crystal films to form high-concentration impurity diffusion layers 708 respectively serving as a source and a drain.
Then, a titanium film is deposited on the high-concentration impurity diffusion layers 708, and a thermal treatment is then conducted to form titanium silicide layers 709 on the high-concentration impurity diffusion layers 708 as shown in FIG. 13(d). Then, non-reacted titanium film portions are removed with a mixture solution of sulfuric acid, hydrogen peroxide and water, or the like.
According to the MOS-transistor fabricating method above-mentioned, the high-concentration impurity diffusion layers respectively serving as a source and a drain are formed at positions upper than the transistor channel region, and only the low-concentration impurity diffusion layers are present in side of the silicon substrate. Thus, shallow junction is substantially formed to provide a transistor having characteristics excellent in short channel effect.
Further, the low-resistance titanium silicide layers are formed on the silicon single-crystal films grown on the silicon substrate. Accordingly, by increasing the thickness of the silicon single-crystal films, the titanium silicide layers can also be increased in thickness. This can lower the parasitic resistance.
According to the MOS transistor fabricating method above-mentioned, however, the treatment temperature is set as low as about 600° C. for example in order to grow, with good crystallinity, the silicon single-crystal films which will result in high-concentration impurity diffusion layers. This extremely increases the period of time during which the silicon single-crystal films are grown. This disadvantageously lowers the fabrication through-put, resulting in reduction in mass-productivity. Such a problem is generally encountered when silicon single-crystal films are formed by epitaxial growth.